1. Field of the Invention
The present invention relates to memory circuits. More particularly, the present invention relates to a cache within a microprocessor configured to include memory cells with preprogrammed data.
2. Background
Improvements in microprocessor designs has lead to microprocessors with a high operating frequency. Current microprocessor designs exceed operating frequencies of 100 megahertz (xe2x80x9cMHzxe2x80x9d). However, the increase in operating frequency has not lead to excepted performance gains. One of the main components affecting performance gains is created by the microprocessor execution units idling during delays in external memory access. The delays in external memory access are caused by the inductive losses associated with off chip transmissions. The delays in external memory access are also caused by the conventional design characteristics of static random access memory (xe2x80x9cSRAMxe2x80x9d) cells and dynamic random access memory (xe2x80x9cDRAMxe2x80x9d) cells.
To counteract the performance losses associated with external memory access conventional microprocessor designs developed cache systems. The cache systems store copies of external data internal to the microprocessor, thus avoiding the performance loss created by accessing external memory. One disadvantage of the conventional cache system is that the cache systems requires consistent updating to ensure data coherency. Because the updating process requires access to external memory intermittent delay cycles still exists within the microprocessor.
FIG. 1 illustrates a prior art cache system. Processor 100 is coupled to external memory 120 via XBUS 130. Using XBUS 130, processor 100 is able to store and retrieve data from external memory 120. Processor 100 also includes cache 110. Cache 110 is used to store copies of data included in external memory 120, thus reducing processor 100 access to external memory 120. By reducing the frequency of access to external memory 120, processor 100 reduces idle cycles, thus increasing the throughput of executions within processor 100.
External memory 120 includes data 140 and data 150 located in non-adjacent address of external memory 120. For one embodiment data 140 and data 150 include fixed data that is used in many iterations of a sequence of instructions. That is, this fixed data is repeatedly used. The fixed data may include an instruction or executable data. During execution of the sequence of instructions, processor 100 must consistently update cache 110 with new data to ensure cache 100 and external memory 120 coherency. During this updating process a current copy of data 140 or data 150 within cache 110 may be flushed. However, because data 140 and data 150 are frequently used during execution of instructions, cache 110 must repeatedly access external memory 120 and re-copy data 140 or data 105 as required by the sequence of instruction. Accordingly, frequent access to external memory 120 to update cache 110 reduces the performance gains of including a cache within a processor 100.
Some processors use a write back cache to counteract the performance loss of consistent cache updating. A write back cache delays time intensive memory updates by storing new data within the cache for a given time period prior to external memory updates. However, write back caches require a complicated controller to track data between the cache and main memory. Further, write back caches are unable to store repetitive data or instruction sequences permanently. Accordingly, write back caches do not provide any performance gains for processors that execute a particular code consistently. Therefore, what is needed is a cache wherein a segment of memory cells are configurable to store pre-programmed data. Also, what is needed is to have the segment of memory cells operate as typical memory cells when the pre-programmed data is not required. While some prior systems have allowed a segment of memory cells to operate as read-only memory or as random access memory, these prior systems typically require careful control of transistor sizes in designing a memory cell.
In one embodiment, the present invention concerns a cache including a plurality of first and second memory cells, an addressing circuit, an enable circuit, and an output circuit.
The second memory cells are configured to store data in a first mode and a second mode. The first mode involves a normal operation wherein the first and second memory cells store and retrieve data similarly. The second mode involves the retrieval of preprogrammed data within the second memory cells. When cache data is accessed, the addressing circuit selects a segment of the cache based on address inputs. Using the output circuit the cache stores or retrieves data from the selected segment of the cache. Dependent on the distribution of memory cells, a given selected segment includes first memory cells and/or second memory cells.
For one embodiment, the enable circuit uses predetermined addresses to determine whether second memory cells within a selected segment of the cache are in first mode or second mode. For alternative embodiments, the enable circuit uses a separate enable signal to determine whether second memory cells within a selected segment of the cache are in first mode or said mode.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows.